1. Field of the Invention
The present invention relates to a start conicidence circuit of asynchronous signals, more particularly to a concidence circuit for coinciding start of two timing generators at an arbitrary point which generators are operated asynchronously when a complete asynchronous test is carried out for an asynchronous memory such as a dual port RAM (hereinafter referred to as two-ports memory).
2. Description of Prior Art
An arrangement of a conventional start coincidence circuit of asnynchronous signals will be described with reference to FIG. 3.
Designated at 1A and 1B are control units, 2 is a synchronous generator, 3A and 3B are signal generators, 4 is a synchronous control unit, 5 is a synchronous signal, 6A and 6B are reference signals, 7A and 7B are memories, 8A and 8B are counters, 9A is a A port and 9B is a B port. The arrangement of FIG. 3 is disclosed in FIG. 1 of Japanese Patent Laid-Open Publication No. 64-59174.
In FIG. 3, the signal generators 3A and 3B having different frequencies are forced to start to issue their reference signals 6A and 6B by the sysnchronous generator 2 and the synchronous control unit 4 at a fixed time. That is, the sysnchrnous signal generator 2 and the synchronous control unit 4 control the control units 1A and 1B, the signal generators 3A and 3B, the memories 7A and 7B and the counters 8A and 8B so that the reference signals A and B which are asynchronous with each other may start at the fixed time.
A circuit of the conventional synchronous control unit 4 will be described with reference to FIG. 4.
Designated at 41 to 45 are gates, 46 and 47 are flip-flops (hereinafter referred to as FFs).
Operations of the circuit in FIGS. 3 and 4 will be described with reference to FIG. 5.
FIG. 5(a) shows a waveform of the reference signal 6A and FIG. 5(b) shows a waveform of the reference signal 6B.
FIG. 5(c) shows a waveform of 5 which outputs a waveform synchronous with the reference signal 6A at two cycles prior to the cycle of the reference signal 6A where the reference signals 6A and 6B are forced to coincide with each other at the fixed time.
FIG. 5(d) shows a waveform of the FF 46 which is output at one cycle behind the synchronous signal 5.
FIG. 5(e) shows a waveform of the FF 47 which is ouput at the time of issuance of the reference signal 6B after the signal 62 of FIG. 5(a) is issued.
FIG. 5(f) shows a waveform which is synchronous with the reference signal 6B before the time of issuance of the signal 63 in FIG. 5(a), but at the time of issuance of the signal 63 in FIG. 5(a), the reference signal 6B coincides with the reference signal 6A since the reference signal 6B is gated by the AND gate 44, namely, at the time when the FF47 issues a high signal.
In FIG. 3, the reference signal 6A issued by the signal generator 3A is supplied to the synchronous control unit 4 and is further supplied to the counter 8B by way of the gate 41, the FF 46, the gate 43 and the gate 45. In the gate 45, the reference signal 6A and the signals from the gate 41, the FF 46, the gate 42, the FF 47 and the gate 44 are ORed, consequently the reference signal 6A can be operated only on the order of 16 ns (60 MHz) in the conventional start coincidence circuit of asynchronous signals.